Chinese chipmakers pay a steep price to bypass EUV restrictions

Chinese memory maker CXMT produces only about one-third as many bits per wafer as Western rivals, according to a June report by Morgan Stanley. This efficiency gap stems from export controls that prevent Chinese firms from acquiring ASML’s extreme ultraviolet lithography machines. Companies like SMIC and CXMT rely on older deep ultraviolet equipment, which requires exposing chip layers multiple times to achieve advanced densities. The process works, but it inflates production costs and reduces output per wafer.

ASML is the sole manufacturer of EUV machines, which use 13.5nm-wavelength light to print fine features on processors. Analysts estimate the technological gap between China and the West in this area is five years or more. Despite the barrier, Chinese firms have advanced further than expected. A 2023 teardown of the Huawei Mate 60 Pro revealed its Kirin 9000S processor was built by SMIC using a second-generation 7nm-class process without EUV. Recent analysis suggests SMIC has since moved its DUV-based process closer to 5nm density levels, though it still trails TSMC and Samsung.

The technical solution involves multiple patterning. Instead of printing a complex layer in a single pass, manufacturers split the design into several simpler patterns and build the layer step by step. Chris Mack, co-founder and CTO of Fractilia, noted that industry standards suggest three exposures on a 193 immersion tool cost roughly the same as one EUV exposure. However, at four masks, EUV becomes the cheaper option. Mack warned that the ability to make a chip without EUV often ignores these underlying trade-offs.

Precision is a major challenge with this method. Each new pattern must align perfectly with previous etchings, so additional exposures accumulate overlay errors and process variation. Designers often add extra space around features to compensate, which enlarges the chip and reduces the number of usable dies per wafer. Since wafers cost tens of thousands of dollars, this reduction in density is expensive. Mack emphasized that manufacturers sell dies, not wafers, making efficiency a primary concern.

The memory sector shows clear signs of this efficiency gap. Morgan Stanley called lithography access a hard ceiling for Chinese memory development. Mack added that process node labels like 5nm or 3nm have limited meaning on their own. He stated that SMIC’s N+3 process, while a step forward, is less scaled than established 5nm processes from Samsung and TSMC. The bank expects CXMT to move to 1-alpha DRAM for HBM3e without EUV, a transition it deems achievable.

DUV technology still has room for improvement. Micron developed its 1-alpha DRAM without EUV using multiple patterning and tight process control. Mack said Micron pushed 193nm technology farther than other memory makers. Douglas Fuller, a researcher at Copenhagen Business School, expects advanced packaging will allow firms to use DUV for the latest DRAM generations by the end of the decade. However, Micron eventually used EUV for its 1-gamma DRAM, which delivers over 30% greater bit density per wafer than the previous generation.

Chinese chipmakers can continue to push DUV limits by accepting larger dies, poorer yields, or longer manufacturing times. They can also add capacity to offset efficiency losses. Morgan Stanley assumes CXMT will stay on 1-alpha without EUV but will increase its share of global DRAM bit supply from 14% in 2026 to 16% in 2028 through new capacity. The bank projects China’s AI chip self-sufficiency will rise from 42% in 2025 to 70% by 2030, even as gaps persist in EUV, HBM, and advanced software.